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However, the programming and timing analysis of multicores is non-trivial due to inteferences that cores suffer from when accessing shared resources. Without a disciplined approach to the parallel programming of multicores, the understanding and debugging of multicore systems becomes difficult. Thus, we aim to develop a new language called FORE-C to enable the deterministic parallel programming of multicores. To guarantee the timing behaviour of FORE-C programs, we will develop an efficient static analysis method to compute precise execution times.
For experimentation purposes, an extensible multicore simulator will be created to execute benchmark programs and report runtime statistics. We will demonstrate that programs written in FORE-C , while being deterministic, will still benefit from multicore execution. The current method of programming the PRET architecture is to create and compile a C program for each hardware thread.
We will investigate the use FORE-C to offer a centralised programming model where a parallel program is mapped to the available hardware threads. We also expect to benefit from the design considerations of the proposed PRET architecture for time predictability and execution performance.
In particular, they have a worldwide recognized expertise is the areas of formal design methods, synchronous programming languages, semantics, and compilers. His research interests include the design of reactive systems, with a special concern for distributed implementation, fault-tolerance, reliability, formal verification, and discrete controller synthesis. He has published 50 papers in international journals and conferences.
He is associate editor of the Journal of Embedded Systems and has been member of several conference programme committees. He studied computer science and graduated from both the University of Karlsruhe and the Computer Science Engineering School at Grenoble Ensimag in He worked as a graduate researcher at Verimag and received his PhD at the University of Grenoble in His research interests include component-based design of embedded systems, and in particular the development of techniques for correctness by construction of heterogeneous systems.
He is a specialist of formal methods, in particular static analysis, abstract interpretation, and model checking. He is the main architect and designer of the several widely used tools and software libraries: Apron a set of abstract domain libraries sharing the same interface with its Interproc demonstration interprocedural analyzer, NBac Numerical and Boolean Automaton Checker: a verification tool based on dynamic partitioning to verify safety properties of programs or systems, connected to Lustre and hybrid automata , and RAPTURE Reachability Analysis of Probabilistic Transition systems by sUccsessive Refinements: a verification tool for finite-state probabilistic systems.
His PhD topic is the SystemJ programming language. The ACEI team Auckland Centre for Embedded Intelligence at the University of Auckland focuses on formal methods for embedded systems, tools for design and computer execution platforms architectures that support the systems with formal foundations.
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With respect to the AFMES project, the ACEI team invented reactive processors , architectures that directly interact with the environment without needing interrupts, and that are time-triggered in nature. One key property of reactive processors is that they are inherently non-speculative and hence time-predictable. In this project we seek to develop reactive execution platforms for PRET-C, thus bringing time-predictability to the widely used C language.
The ACEI team has significant contributions in real-time programming languages and in formal methods for embedded systems. The SystemJ language is accompanied with a compiler that implements the formal semantics of the language and guarantees equivalence between the design and its implementation. To our knowledge, SystemJ is the first system level language that a designer can use to implement real-life GALS systems. Zoran Salcic is a professor of computer systems engineering at the University of Auckland. He made original contributions and published more than journal and conference papers, books and book chapters, as well as major technical reports in the areas of complex digital systems design, custom-computing machines, reconfigurable systems, FPGAs, processor and computer systems architectures, embedded systems and their implementation, design automation tools for embedded systems, hardware-software co-design, new computing architectures, and models of computation for heterogeneous embedded systems.
His main research interests are in the areas of real-time embedded systems, formal verification and validation of hardware-software systems and computer architecture. He has published over 60 papers in refereed journals and conferences. Within the AFMES project, he focused on the issues of time predictable programming language and execution architectures. His PhD topic is defining and implementing run-time support as extension of the operating systems for languages that have formal foundation.
He has designed a library that supports processes that create GALS systems above operating system abstraction. His PhD research involves the design of FORE-C , a deterministic synchronous parallel programming language, and its implementation for multicore systems with attention to timing analysis using reachability. His PhD work included the formal modelling and automatic code synthesis of IEC function blocks. We believe that this complementarity shall allow us to leverage on both sides' expertise fields to achieve the goals of the AFMES project. In particular, the research effort shall be evenly distributed between both teams.
The overall aims of our first research axis will be broken down into the following specific goals. The overall aims of our second research axis will be broken down into the following specific goals. The overall aims of our third research axis will be broken down into the following specific goals.
Significant progress has been made on this aspect of the project in The most significant contributions of this work are summarized below:. The proposed approach uses a simple but expressive representation based on labeled transition systems LTS to describe protocols, specifications and converters. The representation for protocols captures both the control and data exchange aspects of IP protocols precisely, and is timing accurate. Moreover, many formal methods require LTS-like representation. We allow the user to model the desired behavior correctness of the converted system using two types of specifications -- control and data:.
A key feature of the model for control specifications is that we allow specifications to describe only relevant behavior s of the protocols. A control specification is satisfied by a collection of IPs if their projected behavior s are consistent with some behavior s of the specification. This projection-based approach allows the user to write succinct specifications, independent of detailed knowledge of the protocols unlike previous techniques. Data specifications bound the data channels that the protocols communicate through.
Our approach can handle multiple data channels that can have multiple reader and writer protocols connected to them. These specifications are simple and intuitive to create but at the same time enable more flexible and expressive specifications than the existing techniques found in the literature.
The proposed algorithm can handle multiple protocols sharing different types of control signals such as uncontrollable, buffered and converter-generated signals. Uncontrollable signals are also used to model and handle non-determinism in the environment as well as within protocols themselves. We propose specification-enforcing refinement SER as a relation between protocols and specifications describing the maximal non-deterministic converter under which the protocols satisfy the specification. We prove that the presence of an SER is the necessary as well as a sufficient condition for converter synthesis.
The proposed approach has polynomial complexity in the sizes of the protocols and specifications.
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We employ a game theoretic algorithm to compute the SER. Our SER technique allows the incremental design of SoCs, where protocols and specifications are added progressively. We prove that incremental design is mathematically sound, and that the converted system obtained from a previous stage of conversion can be reused in a subsequent stage. We have demonstrated the generality of our approach by showing that some current approaches [Avnit et al, ; Passerone et al ] are restricted cases of our formulation.
We have presented a protocol conversion tool, SoCConvert, based on the proposed technique. In addition, the previous conversion framework developed at ACEI employing CTL specifications [Sinha et al, ], has been extended to include the concepts of maximality and incremental design that were studied during the formulation of the above framework.
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Other extensions to this work include handling full-CTL specifications before that, only negative-normal form CTL was accepted , and proof of incremental synthesis. The following table summarizes the related approaches found in the litterature and compares with our own SER-based approach:. Two submissions are planned from the work that has been done on incremental converter synthesis: A conference and a journal paper are in preparation. SystemJ allows multiple synchronous islands called clock-domains to run together asynchronously, thereby resulting in a GALS execution model.
SystemJ is accompanied with a compiler based on the Asynchronous GRaph Code AGRC format, targeting multiple different execution platforms, ranging from desktops and servers to purpose built reactive processor architectures. We have developed substantial applications with SystemJ, e. Our work on reactive processors, supporting asynchronous and in particular the GALS execution model is also the very first. Our design is a multi-core architecture including; 1 a processor capable of directly executing the AGRC intermediate format, and 2 any data-processor capable of executing the data-driven computations.
Furthermore, our approach is shown to be scalable to a large number of cores, a criteria, which was explored unsuccessfully in previous reactive processor design attempts. Finally, our approach of supporting direct execution of the intermediate format rather than the language constructs makes the processor available to other system level language such as Esterel, which is a subset of SystemJ.
We have successfully designed and implemented a new programming language called DSystemJ , which is a conservative extension of SystemJ.
FORMAL METHODS: BENEFITS, CHALLENGES AND FUTURE DIRECTION
It is primarily aimed at dynamic distributed systems, which are connected via networks. DSystemJ adopts the GALS model of computation Globally Asynchronous Locally Synchronous , and is equipped with a rigorous mathematical semantics allowing for potential formal verification of dynamic distributed systems. DSystemJ allows runtime forking and destruction of processes and of their communication channels, reconfiguration of the system topology, and mobility of processes across networks and physical machines. Although currently targeted at desktop and server based systems, the concepts introduced in DSystemJ are equally applicable to dynamic Network on Chip NoC systems.
DSystemJ introduces five new syntactic constructs to allow the design of dynamic systems with ease. Constructs such as send and receive are used to communicate via channels between these asynchronous processes. Computational modeling of the EGFR network elucidates control mechanisms regulating signal dynamics. BMC Syst Biol. A peptide filtering relation quantifies MHC class I peptide optimization.
October; 7 10 :e Bortolussi L, Policriti A. Shape Calculus. Scientific Annals of Computer Science. BioAmbients: an abstraction for biological compartments. Methods in Molecular Biology. Fisher J, Harel D. Hybrid Systems and Biology. Kauffman S. Metabolic stability and epigenesis in randomly constructed genetic nets. J Theor Biology.